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HY62KF08802B Series
1Mx8bit full CMOS SRAM
Document Title
1M x 8bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
Revision History
Revision No History Draft Date Remark
00
Initial Draft
Jan.19.2002
Preliminary
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.00 / Jan.02 Hynix Semiconductor
HY62KF08802B Series
DESCRIPTION
The HY62KF08802B is a high speed, super low power and 8Mbit full CMOS SRAM organized as 1M words by 8bits. The HY62KF08802B uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
FEATURES
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup -. 1.2V(min) data retention * Standard pin configuration -. 44pin 400mil TSOP-II (Forward)
Product No. HY62KF08802B-I
Voltage (V) 2.7~3.6
Speed (ns) 55/70
Operation Current/Icc(mA) 2
Standby Current(uA) SL LL 12 30
Temperature (C) -40~85
Note 1. I : Industrial 2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
ROW DECODER
A4 A3 A2 A1 A0 /CS1 NC NC I/O1 I/O2 Vcc Vss I/O3 I/O4 NC NC /WE A19 A18 A17 A16 A15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 /OE CS2 A8 NC NC I/O8 I/O7 Vss Vcc I/O6 I/O5 NC NC A9 A10 A11 A12 A13 A14
A0
I/O1
SENSE AMP
COLUMN DECODER
ADD INPUT BUFFER
PRE DECODER
DATA I/O BUFFER
MEMORY ARRAY 1M x 8
WRITE DRIVER
BLOCK DECODER
I/O8
A19
/CS1 CS2
TSOPII (Forward)
/OE /WE
PIN DESCRIPTION
Pin Name /CS1, CS2 /WE /OE I/O1~I/O8 Pin Function Chip Select Write Enable Output Enable Data Inputs/Outputs Pin Name A0~A19 Vcc Vss NC Pin Function Address Inputs Power (2.7~3.6V) Ground No Connection
Rev.00 / Jan.02
2
HY62KF08802B Series
ORDERING INFORMATION
Part No. HY62KF08802B-SD(I) HY62KF08802B-DD(I) Note 1. I : Industrial Speed 55/70 55/70 Power SL-part LL-part Temp. I I Package TSOP-II TSOP-II
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to VCC+0.3V -0.3 to 4.6 -40 to 85 -55 to 150 1.0 260 * 10 Unit V V C C W C*sec Remark
HY62KF08802B-I
Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 H X L L L CS2 X L H H H /WE X X H H L /OE X X H L X Mode Deselected Deselected Output Disabled Read Write I/O Pin (I/O1~I/O8) High-Z High-Z High-Z DOUT DIN Power Standby Active Active Active
Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH)
Rev.00 / Jan.02
2
HY62KF08802B Series
RECOMMENDED DC OPERATING CONDITION
Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31. Typ 3.0 or 3.3 0 Max. 3.6 0 Vcc+0.3 0.6 Unit V V V V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40C to 85C Sym Parameter ILI Input Leakage Current ILO Icc Output Leakage Current Operating Power Supply Current Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS1 = VIH or CS2 = VIL or /OE = VIH or /WE = VIL /CS1 = VIL, CS2 = VIH VIN = VIH or VIL, II/O = 0mA /CS1 = VIL, CS2 = VIH 3.0~ 55ns VIN = VIH or VIL, Cycle 3.6V 70ns Time = Min, 2.7~ 55ns 100% Duty, II/O = 0mA 3.3V 70ns /CS1 < 0.2V, CS2 > Vcc-0.2V VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS1 = VIH, CS2 = VIL VIN = VIH or VIL /CS1 > Vcc - 0.2V, 3.0~ SL CS2 < Vss + 0.2V, 3.6V LL VIN > Vcc - 0.2V or SL 2.7~ VIN < Vss + 0.2V 3.3V LL IOL = 2.1mA IOH = -1.0mA Min -1 -1 Typ1. Max 1 1 4 25 20 20 15 3 Unit uA uA mA mA mA mA mA mA
ICC1
Average Operating Current
ISB
Standby Current (TTL Input)
300 0.2 0.2 0.2 0.2 12 30 12 25 0.4 -
uA uA uA uA uA V V
ISB1 VOL VOH
Standby Current (CMOS Input) Output Low Output High
2.4
Note 1. Typical values are at Vcc = 3.0V TA = 25C 2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS1,CS2, /WE, /OE) COUT Output Capacitance (I/O) Note : These parameters are sampled and not 100% tested Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF
Rev.00 / Jan.02
3
HY62KF08802B Series
AC CHARACTERISTICS
TA = -40C to 85C, unless otherwise specified # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Symbol Parameter 55ns Min. Max. 55 10 5 0 0 10 55 50 50 0 45 0 0 25 0 5 55 55 30 20 20 20 70ns Min. Max. 70 10 5 0 0 10 70 60 60 0 50 0 0 30 0 5 70 70 35 25 25 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write
AC TEST CONDITIONS
TA = -40C to 85C, unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm DOUT CL(1) 1728 Ohm
Note 1. Including jig and scope capacitance
Rev.00 / Jan.02
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HY62KF08802B Series
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
tRC ADDR tAA tACS /CS1 tOH
CS2 tCHZ(3) /OE tOLZ(3) Data Out High-Z tCLZ(3) Data Valid tOE
tOHZ(3)
READ CYCLE 2 (Note 1,2,4) tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3 (Note 1,2,4)
/CS1
CS2 tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /CS1 and CS2 are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active.
Rev.00 / Jan.02
5
HY62KF08802B Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC ADDR tWR(2) tCW /CS1
CS2
tAW tWP
/WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
tWC ADDR tAS /CS1 tAW CS2 tCW tWR(2)
tWP /WE tDW Data In High-Z Data Valid tDH
Data Out
High-Z
Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2. 2. tWR is measured from the earlier of /CS1or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
Rev.00 / Jan.02
6
HY62KF08802B Series
DATA RETENTION ELECTRIC CHARACTERISTIC
TA = -40C to 85C Symbol Parameter VDR Vcc for Data Retention Test Condition /CS > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS > Vcc - 0.2V or VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min 1.2 SL LL 0 tRC Typ1. 0.1 0.1 Max 3.6 6 20 Unit V uA uA ns ns
Iccdr
Data Retention Current Chip Deselect to Data Retention Time Operating Recovery Time
tCDR tR
See Data Retention Timing Diagram
Notes: 1. Typical values are under the condition of TA = 25C. 2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM 1
VCC 2.7V tCDR DATA RETENTION MODE tR
VIH VDR CS1>VCC-0.2V /CS1 VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE tCDR CS2 VDR tR
VCC 2.7V
0.4V VSS CS2<0.2V
Rev.00 / Jan.02
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HY62KF08802B Series
PACKAGE INFORMATION
44pin 400mil Thin Small Outline Package Forward (D)
#44
#23
UNIT : INCH(mm)
Max. Min.
#1
#22
0.470(11.938) 0.462(11.735)
0.729(18.517) 0.721(18.313)
0.047(1.194) 0.039(0.991)
0.0083(0.21) 0.0047(0.120)
0.404(10.262) 0.396(10.058)
0.10MAX 0.004MAX 0.016(0.4) 0.012(0.3) 0.0315(0.800) BSC 0.0059(0.150) 0.002(0.050) 0.0235(0.597) 0.0160(0.406) 0~5
Rev.00 / Jan.02
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HY62KF08802B Series
MARKING INFORMATION
Package
h y Y O n 6 R i 2 E
Marking Example
x K A F 8 8 0 2 y B y c w s w s p t
TSOP-II (Forward)
H K
Index
* hynix * yy * ww *p * HY62KF8802B *c : hynix Logo : Year ( ex : 02 = year 2002, 03 = year 2002 ) : Work Week ( ex : 12 = ww12 ) : Process Code : Part Name : Power Consumption -D -S : Speed - 55 - 70 *t : Temperature -I : Origin Country : 55ns : 70ns : Industrial ( -40 ~ 85 C )
: Low Low Power : Super Low Power
* ss
* KOREA
Note - Capital Letter - Small Letter
: Fixed Item : Non-fixed Item (Except hynix)
Rev.00 / Jan.02
9

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